/* $Author: karu $ */
/* $LastChangedDate: 2009-03-04 23:09:45 -0600 (Wed, 04 Mar 2009) $ */
/* $Rev: 45 $ */
module rf (
           // Outputs
           read1data, read2data, err,
           // Inputs
           clk, rst, read1regsel, read2regsel, writeregsel, writedata, write
           );
   input clk, rst;
   input [2:0] read1regsel;
   input [2:0] read2regsel;
   input [2:0] writeregsel;
   input [15:0] writedata;
   input        write;

   output [15:0] read1data;
   output [15:0] read2data;
   output        err;
   
   wire[7:0] en; //write enable of each rf_cell
   reg[7:0] dec; //output of writeregsel decoder
   wire[15:0] mux_in[0:7];

   rf_cell cell0( .data_out(mux_in[0]), .data_in(writedata), .en(en[0]), .clk(clk), .rst(rst));
   rf_cell cell1( .data_out(mux_in[1]), .data_in(writedata), .en(en[1]), .clk(clk), .rst(rst));
   rf_cell cell2( .data_out(mux_in[2]), .data_in(writedata), .en(en[2]), .clk(clk), .rst(rst));
   rf_cell cell3( .data_out(mux_in[3]), .data_in(writedata), .en(en[3]), .clk(clk), .rst(rst));

   rf_cell cell4( .data_out(mux_in[4]), .data_in(writedata), .en(en[4]), .clk(clk), .rst(rst));
   rf_cell cell5( .data_out(mux_in[5]), .data_in(writedata), .en(en[5]), .clk(clk), .rst(rst));
   rf_cell cell6( .data_out(mux_in[6]), .data_in(writedata), .en(en[6]), .clk(clk), .rst(rst));
   rf_cell cell7( .data_out(mux_in[7]), .data_in(writedata), .en(en[7]), .clk(clk), .rst(rst));

   assign read1data = mux_in[read1regsel];
   assign read2data = mux_in[read2regsel]; //muxes

   //decoder
   always @(writeregsel)begin
       case(writeregsel)
           3'b000: dec = 8'h01;
           3'b001: dec = 8'h02;
           3'b010: dec = 8'h04;
           3'b011: dec = 8'h08;
           3'b100: dec = 8'h10;
           3'b101: dec = 8'h20;
           3'b110: dec = 8'h40;
           3'b111: dec = 8'h80;
       endcase
   end
   
   assign en = dec & {8{write}};

endmodule
// DUMMY LINE FOR REV CONTROL :1:
